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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12684

Title: Hardware realization of a novel Automatic Censored Cell Averaging CFAR detection algorithm using FPGA
Authors: Alsuwailem, A.
Alshebeili, S.
Alhowaish, M.
Qasim, S.M.
Keywords: Alarm systems; Detectors; Parallel architectures; Radar target recognition; Signal detection; Signal processing; Tracking radar
Issue Date: 2008
Publisher: IEEE
Citation: International Conference on Signal Processing Proceedings, ICSP 2008, Article number 4697155, Pages 398-401
Abstract: design and field programmable gate array (FPGA)-based realisation of automatic censored cell In this paper we present hardware realization of a novel Automatic Censored Cell Averaging (ACCA) Constant False Alarm Rate (CFAR) detection algorithm based on Ordered Data Variability (ODV) using Field Programmable Gate Array (FPGA). This algorithm has been recently proposed in the literature for radar target detection in non-homogeneous environments. The unknown background level can be estimated by dynamically selecting a suitable set of ranked reference window cells and by doing successive hypothesis tests. The ACCA-ODV based CFAR detector does not require any prior information about the background environment and uses the variability index statistic as a shape parameter to reject or accept the ordered cells under investigation. Recent advancements in modern FPGAs and availability of sophisticated electronic design tools have made it possible to realize the ACCA-ODV CFAR detector in a cost-effective way. The designed hardware is modular and has been physically realized in Altera Stratix II FPGA device. © 2008 IEEE.
URI: http://hdl.handle.net/123456789/12684
Appears in Collections:College of Engineering

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