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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12706

Title: VLSI architecture for fast computation of third-order cumulants for two-dimensional signals
Authors: Musallam, Ziad H.,
Ahmed, Rana E.,
Alshebeili, Saleh A.
Keywords: Algorithms; Computational complexity; Computational methods; Estimation; Fourier transforms; Parallel processing systems; Real time systems; Statistics; Systolic arrays; Time series analysis
Issue Date: 2000
Publisher: IEEE, Piscataway, NJ, United States
Citation: Canadian Conference on Electrical and Computer Engineering Volume 1, 2000, Pages 322-326
Abstract: Higher-order statistics or cumulants, and their associated Fourier transforms, have been established as powerful analytical tools in modern signal processing. To achieve real-time performance in estimating cumulants directly from the incoming time-series data, it is necessary to design a VLSI implementable parallel architecture that speeds up the estimation process. This paper presents a computationally efficient VLSI architecture for computing third-order cumulants for two-dimensional signals. Specifically, the third-order cumulants estimation algorithm is first reformulated so that any redundancy due to symmetry properties is eliminated, and the inherently available parallelism is revealed and exploited by a suitable architecture. It is based on systolic array implementation and exploits parallelism, pipelining, and regular cell structures. The system architecture consists of (3q2+9q+2) processing elements (PEs), where q is the maximum lag of third-order cumulant sequence. Performance in terms of speedup and efficiency is evaluated.
URI: http://hdl.handle.net/123456789/12706
ISSN: 08407789
Appears in Collections:College of Engineering

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