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Please use this identifier to cite or link to this item:
http://hdl.handle.net/123456789/12750
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| Title: | VLSI architecture for a low complexity algorithm for intraframe sub-band coding of HDTV images |
| Authors: | Al-Asmari, Awad Kh.,
Ahmed, Rana Ejaz |
| Keywords: | Algorithms; CMOS integrated circuits; Computational complexity; Electric network synthesis; High definition television; Optimization; Signal filtering and prediction; VLSI circuits |
| Issue Date: | 1994 |
| Publisher: | IEEE, Piscataway, NJ, United States |
| Citation: | Digest of Technical Papers - IEEE International Conference on Consumer Electronics Digest of Technical Papers - IEEE International Conference on Consumer Electronics Digest of Technical Papers - IEEE International Conference on Consumer Electronics 1994, Pages 206-207 |
| Abstract: | A VLSI architecture for a low complexity intraframe subband image coding for HDTV signals is presented. The Generalized Quadrature Mirror Filters (GQMFs), which have smaller overall delay, are optimized in order to achieve high coding efficiency. The filter design exploits a symmetry property among different filter coefficients which, in turn, reduces the hardware complexity of the architecture substantially. The architecture is designed with 1 μm CMOS technology using the scalable design rules of MOS Integrated Services Inc. (MOSIS). The VLSI architecture contains approximately 200,000 transistors and it is capable of operating at a speed of 34 MHz. |
| URI: | http://hdl.handle.net/123456789/12750 |
| ISSN: | 0747668X |
| Appears in Collections: | College of Engineering
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