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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12871

Title: Jitter minimization in Digital Transmission using dual phase locked loops
Authors: Telba, A.,
Noras, J.M.
Abou El Ela, M.
AlMashary, B.
Keywords: Computer simulation; Digital communication systems; Optimization; Phase locked loops; Spurious signal noise; Variable frequency oscillators
Issue Date: 2005
Publisher: IEEE
Citation: Proceedings of the International Conference on Microelectronics, ICM Volume 2005, 2005, Article number 1590083, Pages 270-273
Abstract: Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for minimization of timing jitter due to phase locked loops is described. The timing jitter can be minimized using two phase locked loops connected in cascade, where the first one has Voltage Controlled crystal Oscillator (VCXO) to eliminate the input jitter and the second is a wide band phase locked loop. Usually, RMS jitter is used to describe jitter performance of the system and that can be analyzed. Simulation results for the measurement of jitter in both phase locked loop using MATLAB Simulink are presented. The methodology described is also applicable to other types of clock generator. © 2005 IEEE.
URI: http://hdl.handle.net/123456789/12871
Appears in Collections:College of Engineering

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