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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12872

Title: Simulation technique for noise and timing jitter in phase locked loop
Authors: Telba, A.,
Noras, J.M.
El Ela, M.A.
AlMashary, B.
Keywords: Bandwidth; Computer simulation; Electric connectors; Electric potential; Networks (circuits); Phase diagrams; Spurious signal noise; Timing jitter; Variable frequency oscillators
Issue Date: 2004
Publisher: IEEE
Citation: Proceedings of the International Conference on Microelectronics, ICM 2004, Pages 501-504
Abstract: Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for efficiently measuring timing jitter due to phase locked loops is described. Two important parameters, absolute jitter and cycle-to-cycle jitter, used to describe jitter performance can be analyzed. Simulation results for the measurement of jitter in phase locked loop using MATLAB SIMULINK are presented. The methodology described is also applicable to other types of clock generator and oscillators such as LC oscillators, as well as other kinds of noise source such as power supplies. © 2004 IEEE.
URI: http://hdl.handle.net/123456789/12872
Appears in Collections:College of Engineering

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