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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12924

Title: Hardware design and implementation of fixed-width standard and truncated 4x4, 6x6, 8x8 and 12x12-bit multipliers using FPGA
Authors: Rais, M.H.
Keywords: Digital Signal Processing (DSP); Field Programmable Gate Array (FPGA); Spartan-3AN; Truncated Multiplier; VHDL; Virtex-4
Issue Date: 2010
Citation: AIP Conference Proceedings Volume 1239, 2010, Pages 192-196
Abstract: This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT). Remarkable reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The truncated multipliers show significant improvement as compared to standard multipliers. Results show that the anomaly in Spartan-3 AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 device. © 2010 American Institute of Physics.
URI: http://hdl.handle.net/123456789/12924
ISSN: 0094243X
Appears in Collections:College of Engineering

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