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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12926

Title: FPGA implementation of Rijndael algorithm using reduced residue of prime numbers
Authors: Rais, M.H. ,
Qasim, S.M.
Keywords: Cryptography; Design; Field programmable gate arrays (FPGA); Hardware; Integrated circuits; Linguistics; Logic gates; Optical sensors; Technical presentations; Ultrasonic transducers
Issue Date: 2009
Publisher: IEEE
Citation: 2009 4th International Design and Test Workshop, IDT 2009 2009, Article number 5404130
Abstract: This paper describes the Field Programmable Gate Array (FPGA) implementation of Rijndael algorithm based on a novel design of S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-Box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-Box with reduced residue of prime number adds more confusion to the entire process of Rijndael and makes it more complex and immune to algebraic attacks. The target hardware used in this paper is state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices. ©2009 IEEE.
URI: http://hdl.handle.net/123456789/12926
Appears in Collections:College of Engineering

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