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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12927

Title: FPGA design and implementation of fixed width standard and truncated 6x6-bit multipliers: A comparative study
Authors: Rais, M.H.
Keywords: Cosine transforms; Design; Digital signal processing; Digital signal processors; Discrete cosine transforms; Field programmable gate arrays (FPGA); Frequency multiplying circuits; Impulse response; Logic gates; Optical sensors; Signal processing; Standards; Technical presentations; Ultrasonic transducers
Issue Date: 2009
Publisher: IEEE
Citation: 2009 4th International Design and Test Workshop, IDT 2009 2009, Article number 5404081
Abstract: This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The power and area of truncated 6x6-bit multiplier shows significant improvement as compared to standard 6x6-bit multiplier. For Xilinx Spartan-3AN (XC3S700ANFGG484-5) FPGA device, truncated multiplier shows a reduction in power and area by 45% and 67% respectively as compared to standard multiplier. ©2009 IEEE.
URI: http://hdl.handle.net/123456789/12927
Appears in Collections:College of Engineering

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