FPGA based realization of a reduced complexity high speed decoder for error correction

Abstract

A chip for high speed two bit error correction in the received signal has been designed and implemented on a Xilinx FPGA using VHDL. The design is based on a modified Step - by - Step decoding algorithm which does not require the calculation of the error location polynomial. The use of complex computation - intensive inverse operations is also avoided. Efforts have been made for reducing the complexity of the decoder. A modified circuit has been used for multiplication of field elements within the Galois field. For squaring the field elements within the Galois field, a modified square circuit with much less complexity has been successfully designed. The average operation cycle for decoding each received word is just equal to the block length of the coded word. © 2003 IEEE.