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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/13024

Title: A proposed FPGA-based parallel architecture for matrix multiplication
Authors: Qasim, S.M.
Abbasi, S.A
Almashary, B
Keywords: Applications; Hardware; Parallel architectures; Turbo codes
Issue Date: 2008
Publisher: IEEE
Citation: IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS 2008, Article number 4746382, Pages 1763-1766
Abstract: Matrix multiplication is a computation intensive operation and plays an important role in many scientific and engineering applications. For high performance applications, this operation must be realized in hardware. This paper presents a parallel architecture for the multiplication of two matrices using Field Programmable Gate Array (FPGA). The proposed architecture employs advanced design techniques and exploits architectural features of FPGA. Results show that it provides performance improvements over previously reported hardware implementation. FPGA implementation results are presented and discussed. © 2008 IEEE.
URI: http://hdl.handle.net/123456789/13024
Appears in Collections:College of Engineering

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