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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/15088

Title: LOW POWER ASIC DESIGNS FOR FAST HANDOFF IN
Authors: Ridha OUNI
Keywords: IEEE 802.11, Handoff, MAC, design, ASIC
Issue Date: 2009
Publisher: International Journal of Computers, Systems and Signals
Abstract: The Handoff process is a key problem in many wireless network processing applications. Current implementations of this process using software implementation are time consuming and cannot meet the gigabit bandwidth requirements. Implementing this process within the hardware improves the search time considerably and has several other advantages like reducing power consumption. In this paper we present an array based hardware implementation of this time consuming process for network mobility. A new mechanism for mobility management to minimize the handoff latency in IEEE 802.11 wireless local area network is also presented. Compared to the basis model and at 1GHz, this new mechanism allows a profit of 60% in power consumption and 20% in silicon area. Those two designs are described in VHDL at the RTL level language and implemented on an ASIC (Application-Specific Integrated Circuit) and are evaluated in terms of speed, area and power consumption.
URI: http://hdl.handle.net/123456789/15088
Appears in Collections:College of Computer and Information Sciences

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